Senior ASIC Design Engineer San Jose, CA

Company: Tbwa Chiat/Day Inc
Location: San Jose
Posted on: November 13, 2024

Job Description:

Ethernovia is fundamentally changing how cars of the future are built by unifying in-vehicle networks into an end-to-end Ethernet system. Founded in 2018, we're inventing the future of automobile's communication! We are transforming automobiles' communication network to enable the autonomous driving, electrical vehicle (EV) and software defined revolutions. Our breakthrough compute, communication, and software virtualization ushers in a new era of car connectivity and capabilities. We bring together, accelerate, and unify the car's cameras/sensors, compute, and outside world to enable new advanced driver assistance features and services.With talented employees on 4 continents, we have filed > 50 patents to date.Join Ethernovia's team to make a lasting impact on the future of mobility. Come share in our success with pre-IPO shares, competitive compensation, and great benefits while growing your knowledge and career with world class talent. We are looking for talented engineers and leaders who have an entrepreneurial spirit and want to drive their design from concept to silicon to their next car.Summary:

• As a Senior ASIC Design Engineer, you will be responsible for all aspects of digital SoC design, from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and static timing analysis to deliver a design meeting target power, performance, and area goals.
• Work with system architects, software, hardware, and verification engineers to plan, architect, design, implement, and deliver advanced automotive communication semiconductors and systems.
• You will be on the leading edge of the development and definition of advanced, high-performance custom silicon that embodies functions from a wide range of protocols, algorithms, and applications.
• Expected to flesh out product definitions with precise specifications of: an ASIC's internal and external interactions, data flow, processing algorithms across a number of disciplines, resource management, and software interfaces.
• You will be a trusted self-starter who can work with very little guidance or oversight.
• This position is located in: San Jose, CAKey Qualifications:
  • BS and/or MS in Electrical Engineering, Computer Science, or related field
  • Minimum 10+ years of ASIC RTL design and/or architecture experience
  • Proven track record with the development of complex SoCs
  • Strong understanding of digital design fundamentals and methodologies
  • In-depth knowledge of Verilog/System Verilog and simulation tools.
  • Self-motivated and able to work effectively both independently and in a teamAdditional Success Factors:Experience in any of the following areas:
    • Networking (Ethernet MAC, PHY, Switching, TCP/IP, security, PCIe and other industry standard protocols)
    • Video standards, protocols, processing
    • Digital signal processing filters
    • Perl, TCL, C/C++, MakePersonal Skills:
      • Collaboration across multidisciplinary and international teams.What You Can Expect From Ethernovia:
        • Technology depth and breadth expansion that can't be found in a large company
        • Opportunity to grow your career as the company grows
        • Pre IPO stock options
        • Cutting edge technology
        • World class team
        • Flexible hours
        • Medical, dental and vision insurance for employees
        • Flexible vacation time to promote a healthy work-life balance
        • Paid parental leave to support you and your familySalary Range:The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $180,000 - $230,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, in addition to base salary and a full range of medical and other benefits.
          #J-18808-Ljbffr

Keywords: Tbwa Chiat/Day Inc, Castro Valley , Senior ASIC Design Engineer San Jose, CA, Engineering , San Jose, California